Data conveyance systems, or data communication systems, are known to comprise a data bus and a plurality of peripheral circuits that access the data bus. In some systems, one of plurality of peripheral circuits is designated as a data control circuit to coordinate access the data bus to prevent several peripheral circuits accessing the data bus at the same time. Yet in other systems, the system may further comprise a data controller module that coordinates access to the data bus. The data bus is typically a digital data bus and may incorporate time division multiplexing (TDM). A TDM digital bus is time divided in to time slots and each time slot has an address based on a time relationship within a frame cycle. For the peripheral circuits to transmit and receive data either to other units or to the data controller, they must be exclusively assigned at least one time slot.
In many applications, the data conveyance system or modular network, physically comprises a card cage with a limited number of connectors such that peripheral, or modular, circuits may be plugged into the card cage. The connectors are usually coupled together by a back plane which also supports the TDM bus. Typically, the time slots are assigned to modular circuits based on their physical location within the card cage. This results because the card cage is hard wired to the back plane such that the first connector typically is allocated the first time slot. This presents a problem in that if a connector is empty or is connected to a modular that does not need to access the TDM bus, at least one time slot is still assigned to the connector, thus wasting at least one time slot.
An alternative to having fixed time slot addresses is to have each modular circuit contain a specific time slot address such that regardless of its position in the card cage it will know which time slot to access in the TDM bus. This presents a problem in that, if DIP switches are used to establish the time slot address, manual operations are required which could result in an error occurring.
Therefore, a need exists for a method and apparatus that eliminates the hard wiring addressing scheme of time slots and also eliminates the need for manual programming of time slot addresses on each module.